1. Field
Example embodiments relate to a semiconductor device having a buried gate electrode and a method of fabricating the same.
2. Description of Related Art
Recently, there has been increasing research on the buried word line cell array transistor (BCAT) in which a word line (WL) may be buried below the surface of a semiconductor substrate using a metal (and not a polysilicon) as a gate electrode in the structure of a conventional recess channel array transistor (RCAT). Unlike a polysilicon gate in a conventional DRAM, a word line having 0.5 F pitch/interval can be formed using a BCAT technique, and accordingly, the area of the cell can be reduced.
FIG. 1 is a cross-sectional view of a semiconductor device comprising a gate structure according to the conventional art.
Referring to FIG. 1, an active region 26 is defined in a substrate 10 by a device isolation layer 12, and a trench 14 is formed in the substrate 10. A gate insulating layer 16 is disposed on the bottom surface and the inner surface of the trench 14. A metal gate electrode 20, which fills the trench 14 on the gate insulating layer 16 and protrudes beyond the substrate 10, is formed. Spacers 24 are formed on both sides of the protruded metal gate electrode 20, and a capping pattern 22 is disposed on the upper surface of metal gate electrode 20. An active region of a source and drain is formed in the substrate adjacent to both sides of the metal gate electrode 20. The metal gate electrode 20 can serve as a gate electrode and a word line.
In the semiconductor device, the metal gate electrode 20 is buried into the substrate 10 and also protrudes beyond the surface of substrate, and accordingly, the spacer 24 for supporting the metal gate electrode 20 is required. Therefore, in the above structure, the semiconductor device having a height corresponding to the protruded portion of the metal gate electrode 20 is formed. Thus, the above structure is not ideal for embodying a thinner device.
A titanium nitride (TiN) metal gate may be formed by a chemical vapor deposition (CVD) method. In order to secure the thermal stability at a temperature above 1000° C., a resistivity of the word line below 40 kohm/line and a superior gate diode integrity (GOI) characteristic is used as the gate electrode of the BCAT. For example, in order to secure a step coverage above 10:1, a TiN layer formed by a chemical vapor deposition (CVD) method using TiCl4 and NH3 is used for forming the metal gate. However, chlorine ions in TiCl4 are diffused into the oxide layers and silicon channels, thereby forming traps in the oxide layers. As a result, degradation characteristics of the oxidation layer occur below −3V, which is in the operation voltage region due to trap assisted tunneling (TAT). As a result, reliability of the device is reduced.
FIG. 2 is a graph illustrating gate voltage-current characteristics of the semiconductor device having a gate structure according to the conventional art.
Referring to FIG. 2, gate voltage-current characteristics of a polysilicon gate electrode according to the conventional art is denoted by Line A, and gate voltage-current characteristics of a gate electrode and a word line formed of titanium nitride (TiN) according to the conventional art as illustrated in FIG. 1 are denoted by Line B. Line B shows a higher current value as compared to Line A for a gate voltage within the range of approximately −3V to −5V, which indicates an increase of the leakage current. The degradation of the oxide layers due to the occurrence of chlorine ions from applying the TiN layer, which is formed using a CVD or an atomic layer deposition (ALD) method, is one of the causes of the problems described above.